1. Field of the Invention
The present invention relates to semiconductor devices including field effect transistors, and, particularly, semiconductor storage devices, and a method of fabricating the same.
2. Description of the Related Art
Demand for the advanced functions of data processors has progressively increased with the evolution of multimedia. Since processes for processing audios and images need to process a large amount of data in a short time, the enhancement of the throughput of a data processor is essential. However, if the data processor has an individual logic chip and an individual memory chip, which are principal components of the data processor, the data path between the logic chip and the memory chip is a bottleneck that obstructs the enhancement of the throughput of the data processor.
A DRAM embedded chip integrally provided with a logic circuit and a DRAM (dynamic random-access memory) on a single chip has been developed to solve the above-noted problem. Techniques relating to such a DRAM embedded chip are mentioned in H. Ishiuchi, et al., IEEE International Electron Devices Meeting, pp. 33-36 (1997). In view of the facility in integrating the components, an SRAM (static random-access memory) comprising memory cells of only logic transistors is preferable for use in a DRAM. However, since each memory cell of SRAM consists of six transistors, the memory cell needs a large cell area, and high cost makes it difficult to form an SRAN of a large capacity.
A proposed memory cell has been proposed which is called a gain cell. This structure is capable of operating even if the number of stored charge of a DRAM cell is reduced. Charges are injected through a write transistor to a storage node and information can be read by virtue of the change of the threshold voltage of a read transistor caused by the stored charge for signal storage. Techniques relating to the present invention include a write transistor formed by polysilicon, mentioned in H. Shichijo, et al., Conference on Solid State Devices and Materials, pp. 265-268 (1984), a read transistor formed by polysilicon, mentioned in S. Shukuri, et al., IEEE International Electron Devices Meeting, pp.1006-1008 (1992), and single-electron memories formed by polysilicon, mentioned in K. Yano, et al., IEEE International Electron Devices Meeting, pp. 541-544 (1993) and K. Yano, et al., IEEE International Solid-state Circuits Conferences, pp. 266-267 (1996). These techniques relate to memory devices that use a single cell for signal storage. Although different from the present invention in the principle of operation and function of the memory cell, those techniques include a general configuration called a TFT configuration having a channel which is thinner than a source and a drain; that is, the bottom of the source/drain region is substantially flush with the thin film channel region.
The reduction of the power consumption of devices, including battery-powered devices such as personal digital assistants, is an important problem. Generally, a semiconductor device consumes most of the power consumed by an apparatus including the semiconductor device, and, hence, the reduction of power consumption of the semiconductor device is required. The current of a transistor in an OFF status is called a leakage current. Since the leakage current is a matter that can affect all the circuit elements on a chip, the current is one of factors of increasing power consumption of a whole semiconductor chip without distinction in case of as to whether the leakage current exists in a logic circuit or a memory circuit. Therefore, the reduction of power consumption of the semiconductor device is required. The inventors have found out that a TFT structure which includes a polycrystalline silicon base having a thin channel region causes a leakage current in the range of 10xe2x88x9218. However, in case of a FET structure in which the thickness of a channel region is thinner than the thickness of a source and/or drain region, the base height of a source and/or drain region is almost the same as the height of a channel thin film region. A gate insulator layer of this structure is deposited by CVD. Therefore, a step between a top surface of a source and/or a drain region and a top surface of a channel region causes a concentration of an electrical field at a top portion of the step. Therefore, a margin of dielectric strength is reduced when a gate insulation layer is thinner. Some parts of a gate insulating film are thick at lower the portion of the above-said step, and, hence, the performance of the transistor deteriorates and it is possible that the short channel effect can become remarkable.
Accordingly, it is an object of the present invention to provide a low-leakage, high-performance semiconductor device.
Another object of the present invention is to provide a semiconductor device that operates at a low power consumption.
As mentioned above, techniques of integrating a logic circuit and a DRAM have been developed and DRAM embedded devices have been marketed. However, there is a problem in the compatibility of logic circuit fabricating processes and DRAM fabricating processes.
First, when the logic fabricating processes and the DRAM fabricating processes have only a few processes in common, many masks and steps are necessary, which increases manufacturing cost. A capacitor forming process, which is the most complicated process among those of fabricating the DRAM, cannot be used for forming the component of the logic circuit. Fast operation is an important capability of the logic circuit, and, hence, the diffusion layer of the MOS transistor of the logic circuit is silicided to reduce the resistance. However, if the diffused layer of the path transistor of the memory cell of the DRAM is silicided, leakage current increases and data retention time decreases greatly. Therefore, a region for the DRAM must be covered during a process for siliciding the diffusion layer of the logic circuit when forming MOS transistors for the circuit, which requires complicated processes.
Secondly, a high-temperature process for forming capacitors of a DRAM entails a problem. Since a DRAM must keep a high S/N ratio, a DRAM must achieve a large storage charge even in the face of continued cell size miniaturization. Therefore, a dielectric film having a high dielectric constant must be employed to keep the capacity in an smaller area. The use of a conventional three-dimensional structure is costly, and, hence, is infeasible, and a dielectric film having a high dielectric constant is indispensable even if a three-dimensional structure is used. A high-temperature process is necessary for forming a dielectric film having a high dielectric constant. For example, when forming a Ta2Os film (tantalum pentoxide film), a high-temperature process is necessary that uses heat on the order of 750xc2x0 C.
The pn junction of a MOS transistor of the logic is formed in a very shallow diffusion layer for miniaturization. An impurity is diffused out in the diffusion layer by a heat treatment, the characteristic of the MOS transistor is deteriorated, and the MOS transistor malfunctions due to punch through. A silicide, such as cobalt silicide, tends to aggregate when heated at a high temperature. When a trench capacitor structure is employed, in which a capacitor is formed in a trench formed in a substrate, capacitors can be formed before forming the MOS transistors of the logic. However, the trench must be very deep and the aspect ratio increases inevitably when the structure is produced by finer pattern.
The problem in keeping stored charge is not only with the embedded chip but also with DRAMs. There is the possibility that a new dielectric material having a high dielectric constant must be developed every time the generation advances after the generation of 1 Gb RAMs with a design rule in the range of 0.18 to 0.14 xcexcm. Thus, a semiconductor memory capable of stably operating even if stored charge is reduced, and capable of being formed in a high level of integration corresponding to that of DRAM in a small area is necessary.
Accordingly, it is a third object of the present invention to provide a semiconductor device integrally provided with a high-performance logic and a memory and capable of being manufactured at a low cost.
The present invention provides a large-scale memory capable of properly operating even if semiconductor devices are produced by more fine pattern.
The present invention is characterized in reading a charge injection or charge emission through a write transistor by the change of the threshold voltage of a read transistor. A logic circuit can be easily combined because there is no need for any new material for securing capacitance for a DRAM. A transistor according to the present invention can be very effectively applied to such a semiconductor device.
According to a first aspect of the present invention, a semiconductor memory cell comprises a source region, a drain region, a channel region of a semiconductor material connecting the source region and the drain region, and a gate electrode for controlling the potential of the channel region, wherein the channel region is formed on an insulating film, and the channel region is disposed on a level corresponding to the upper surfaces of the source region and the drain region with respect to a surface of a substrate.
Preferably, the channel region is a thin semiconductor film of 5 nm or below in thickness. Since the channel region is a very thin semiconductor film, the leakage current is very small. This constitution will be understood by referring to FIG. 1.
According to a second aspect of the present invention, a semiconductor memory cell comprises: a first transistor structure (M2) including a source region of a metal or a semiconductor material, a drain region of a metal or a semiconductor material, a channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode of a metal or a semiconductor material for controlling the potential of the channel region; and a second transistor structure (M1) including a source region of a metal or a semiconductor material, a drain region of a metal or a semiconductor material, a channel region of a semiconductor connecting the source region and the drain region, a gate electrode of a metal or a semiconductor material for controlling the potential of the channel region, and a charge storage region of a metal or a semiconductor material coupled with the channel region by electrostatic capacitance. In this arrangement, the source region of the second transistor structure is connected to a source line, the one end of the source or the drain region of the first transistor structure is connected to the charge storage region of the second transistor structure, and the other end of the source or the drain region of the first transistor structure is connected to a data line.
According to the present invention, a charge storage region (1) and a control electrode (5) of a read transistor are layered, and, hence, the cell can be formed in an area smaller than that of a three-transistor gain cell. Since the channel of a write transistor is a semiconductor thin film formed on an insulating film (134) and a charge leakage path in a channel (3) can be completely depleted, leakage current is far less than that in a device employing an MOS transistor formed on a bulk substrate as a write transistor.
The storage region (1) or the channel (3) of the write transistor can be formed by a self-alignment process in alignment with a word line (5). Thus, the cells of the semiconductor device can be formed by simple processes in small area. Reference characters used in the foregoing description are those used in FIG. 1.